With continuing advances in integrated circuit technology, more and more circuits and circuit elements are being packed into a unit area. As a result, the current density for a unit area continues to increase at the rate of 1.5× to 2× for each generation of technology, e.g. from 130 nm to 90 nm. The increase in current density in turn leads to increase in high current hotspots, and/or large localized current transients.
In the prior art, typically, the top two metal layers of a silicon die are employed to collect the operating current and connect it to the C4 bumps (C4=controlled collapse chip collection). The C4 bumps in turn couple the operating current to the die-package interface of the packaging. Further, in addition to being employed to collect the operating current, the top two metal layers are also used for signal routing.
To accommodate the possible use for signal routing, typically, relatively thin metal wires are used. The relatively thin metal wires are typically organized in a lattice like arrangement, e.g. with the metal wires in the top metal layer arranged longitudinally, and the metal wires in the next metal layer arranged latitudinally. The C4 bumps disposed in the top metal layer are typically arranged in what is known as a “hexagonal” arrangement (a name derived from the relative locations of the neighboring bumps). Viewed from another perspective, the C4 bumps may also be described as being organized in a shifted or offset row/column manner. Due in substance to the relative dimensions of the metal wires and bumps, typically, not all metal wires will connect to a bump.
Experience has shown that the C4 bumps in general do not scale down correspondingly as the technology scale down. Resultantly, the prior art metallization and bump arrangement scheme is expected to have difficulty in handling the expected increase in current density, and the resulting increase in high current hotspots and/or localized current transients.